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30/12/25

High-Speed Via Design and Signal Integrity Analysis with Clarity

This hands-on workshop provides a comprehensive introduction to via design and signal integrity analysis using Clarity. Participants can bring their own (.BRD,OBD++,IPC2581) via design and learn how to import, simulate, and optimize them. The workshop focuses on practical via evaluation using S-parameters and TDR analysis, with hands-on exercises in automatic parameter sweeping, optimality studies, and performance verification.

Who Should Attend:

EE engineers with basic knowledge of PCB design

Workshop Agenda

Lesson 1

Introduction to Via Design and Clarity

  • Overview of Clarity for via analysis.
  • Basics of Signal Integrity (SI) related to vias.
  • How S-parameters and TDR relate to via performance.
Lesson 2

Importing Your Via Design

  • Import your .BRD/ODB++/IPC2581 file into Clarity.
  • Define ports, boundary conditions, and simulation parameters.
  • Configure solver settings and frequency options.
Lesson 3

S-Parameter Analysis for Vias

  • Understanding via S-parameters and their significance.
  • Reading S-parameter plots specific to via performance.
  • Identifying reflection, loss, and crosstalk issues.
  • Optimizing via design based on S-parameter results.
Lesson 4

TDR Analysis for Vias

  • Understanding TDR for vias.
  • Performing TDR measurements in Clarity.
  • Interpreting results to identify impedance mismatches and via defects.
  • Improving via performance based on TDR insights.
Lesson 5

Part 5: Automatic Exploration and Optimization

  • Introduction to Parameter Sweeping in Clarity: varying via dimensions and materials to study SI impact.
  • Optimality Analysis: finding the best design parameters automatically for minimal reflections and loss.
  • Hands-on exercises using yourvia design to run sweeps and optimize performance.
Lesson 6

Hands-On Workshop

  • Participants work on their own via designs.
  • Import, simulate, analyze S-parameters and TDR.
  • Apply parameter sweeps and optimality studies.
  • Troubleshoot via-related SI issues and optimize design.
  • Q&A and discussion of results.
Workshop Outcomes:

By the end of the session, attendees will be able to design and optimize high-speed vias including optimality studies for performance verification.

Attendees will receive a 30-day Clarity evaluation license after completing the workshop.

Registration Information

  • EDA Integrity Solutions Offices, 38 Habarzel St, Tel Aviv
  • 30/12/25
  • 12:30 PM – 5:00 PM
For Additional Information:

Guy: 050-9161134

Revital: 054-5744779

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