Educational Training

Length: 3 days
Digital Badge Available

Course Description
This is the first in a two-series course. It is recommended that you take the Allegro® PCB Editor Intermediate Techniques course after finishing this one. The Allegro PCB Editor Basic Techniques course contains all the fundamental steps for designing a PCB, from loading logic and netlist data to producing manufacturing/NC output. The task-oriented labs show you the combined use of interactive and automatic tools. This course requires the Allegro PCB Designer license or above. This course requires the SPB17.2-2016QIR6(S038) software or later.

Length: 2 days

Course Description
The Allegro® PCB Editor Intermediate Techniques course gives you a deeper understanding of the software, and includes features and tips. You apply constraints, autoroute high-speed designs, and work with differential pairs. In this course, you also explore high-speed design rules, create areas in your design that require different routing rules, and generate testpoints. In the task-oriented labs, you use a combination of interactive and automatic tools. This is the second in a two-course series. You need to complete the Allegro PCB Editor Basic Techniques course before taking this one or have the equivalent work experience.
This course requires the SPB17.2-2016QIR6 software or later.

Length: 1 day

Course Description
This class is designed around more advanced topics and exploration of the tool. This course does not teach basic tool operations. It is required that designers who are not actively using the tool first complete the Allegro® PCB Editor Basic Techniques and the Allegro® PCB Editor Intermediate Techniques courses. In this course, you will explore the use of advanced methodologies available from within the PCB Editor software. You will start with creating multiple cross sections in your design. This is usually required with Flex designs but can also be used in standard PCB designs. You will then explore creating Inter Layer checks. Again, this is a requirement for Flex designs but can also be used in standard PCB designs. Next, you will create via structures. Via structures consists of a series of vias, usually blind and/or buried vias, connected by routing to create a single element that can be used much like a library element. Finally, you will set up your design and run the Backdrilling routine. Backdrilling is a manufacturing technique that can be used to remove stubs created by vias.

Length: 2 days

Course Description
This Engineer Explorer course is designed around advanced topics and exploration of the software. This course does not cover basic operations. If you are not actively using the software, then you need to complete the Allegro® PCB Editor, the Allegro Package Designer, or the Allegro Design Entry HDL Front-to-Back Flow course. In this course, you apply and verify high-speed constraints across a design process. You learn to schedule nets, control impedance on nets, control the propagation delay from your drivers to receivers, and match the propagation delay of driver and receiver pairs

Length: 2 days

Course Description
In this course, you learn how to use the Allegro® PCB Router to perform automatic and interactive routing. You run autorouting, modify design rules, run interactive routing, analyze router log files, fan out a design, and improve manufacturability. You also restrict routing to specific areas of the board and keep signals away from other areas.

Some of the introductory material assumes that you are using the router in conjunction with the Allegro PCB Editor tool for board layout.

Length: 1 day

Course Description
In this course, you learn about different RF PCB front-to-back flows. One popular flow starts from the Agilent Advanced Design System (ADS) toolset. Although you do not use the ADS tool in this course, you learn how to import an IFF file representing the ADS schematic into Allegro® Design Entry HDL (DE-HDL). In another flow, you import the ADS schematic and layout files directly into Allegro PCB Editor. You also create an RF schematic in DE-HDL, merge RF blocks from ADS, and backannotate the DE-HDL schematic with part, property, and connectivity changes made in the RF layout.

Length: 2 days

Course Description
In this course, you use the Allegro® Sigrity™ SI software to develop design rules for high-speed designs. You add the resulting physical and electrical constraints to the design through topology templates. These constraints drive the routing of nets on the printed circuit board. You run preroute and postroute signal simulations to analyze the PCB for reflection, crosstalk, and other high-speed design factors.

Course Description
This course covers Modeling, Simulation and Analysis of Power-Aware Parallel Bus System (DDR3 and DDR4) using the Allegro Sigrity SystemSI - PBA II.

Length: 1 day

Course Description
Participants in this class will utilize the latest simulation and modeling techniques available for the design and analysis of serial data channels. A basic channel with default models is used for the first simulation so 2D eye diagrams, 3D eye diagrams, and bathtub curves can be generated and viewed. Next the participants will modify the analysis options to control the bit rate of the channel and inject distortion and jitter into the channel. IBIS-AMI models will then be discussed and the users will adjust AMI parameters and use a vendor based IBIS-AMI model in the simulation. A pre-route scenario will then be investigated with the TLine Editor being used to create transmission line models and the Via Wizard used to create via models. Finally, a post-route scenario will be covered and PowerSI™ will be used to extract an S-Parameter model from the routed interconnect of a PCB Editor board database.

Course Description
This course first discusses building a simple pre-layout PCB in PowerSI® followed by studying electrical parameters of signal traces reported in the Trace Properties window. Next, electrical parameters of microstrip and stripline traces reported in the Trace Properties window and computed using the closed form expressions are compared.

Length: 3 days

Course Description
This course covers modeling, simulation and analysis of parallel bus systems, and serial link systems using Sigrity™ SystemSI™.

Length: 1 day

Course Description
The Allegro® Sigrity™ PI course covers the Allegro Sigrity PI product, which provides an integrated solution for power delivery analysis, and features integrated Sigrity technology for DC analysis and a Power Feasibility Editor to drive the creation of Power Integrity Constraint Sets. In this course, you run a DC analysis on a PCB to determine the voltage drop seen by the power consuming components on a PCB. You also use the Power Feasibility Editor to select and analyze a set of capacitors and create a decoupling strategy for ICson the board. This strategy is then captured in a power integrity constraint set and is passed back to the design and managed in the Constraint Manager. You also use these power integrity constraint sets to provide placement guidance for placing the decoupling capacitors on the board.

Length: 1 day

Course Description
Sigrity™ PowerDC™ and OptimizePI™ provides a coherent methodology for the analysis of power delivery networks in high-speed printed circuit boards (PCBs). Power-delivery network design includes voltage regulator modules, decoupling capacitors, and power/ground planes. In this course, you use the Sigrity Power Integrity Suite software to analyze a stable power distribution system to support high-speed circuit operation.

Length: 1 day

Course Description
Cadence® OrbitIO™ System Planner helps design teams quickly assess and plan connectivity between the die and package in context of the full system — all within a single-canvas multi-fabric environment. It’s ideal for system architects or anyone responsible for developing the die-to-package interface and coming up with the optimal combination of bump/ball configurations and net assignments. It helps semiconductor companies evaluate route feasibility of the package, as well as develop and communicate a route plan to their package design resources.

Length: 4 days

Course Description
In this course, you use the Allegro® Package Designer system for the design and specification of manufacturing single-chip modules for single-, double-, or multilayered analog and digital packages. You develop a process flow, create cross section and design constraints, construct single-chip module connectivity, and route a design. You also create bond pads, make blind and buried padstacks, and output manufacturing data.

Course Description
In this course, you learn the complete flow of a System in Package (SiP) design, from defining the module outline to placing components, defining a netlist, placement, routing, documentation, and manufacturing output. You also learn the complete design flow for a flip-chip and wire-bonded stacked die module using the Cadence® SiP Layout software.