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DDR4 Design and Analysis with Cadence Sigrity

DDR4 becomes pretty common high-speed source-synchronous interface. We are inviting you to attend half a day workshop that discuss and show DDR4 post-layout simulations with non-ideal power conditions. Synchronous design performance metrics including eye diagrams with detailed timing measurements and compliance kits vs JEDEC standard are available as outputs.
    

Audience
Electrical Engineers and Signal Integrity engineers who wish to learn how to analyze DDR4 interface using Sigrity SystemSI-Parallel Bus Analysis DDR4 Compliance Kit

Agenda
  • DDR4 interface exploration
  • Exploring the tool
  • Exploring a pre-determined topology
  • Setting up the analysis
  • Running the simulation
  • Browsing the results
  • Generating a report
 
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  • EDA Integrity Solutions Ltd

  • Address38 HaBarzel St. Tel Aviv 6971054 Israel
  • Tel(972) 3 6444416
  • Fax(972) 3 6444462
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