Course Description In this course, you use the Allegro® Sigrity™ SI software to develop design rules for high-speed designs. You add the resulting physical and electrical constraints to the design through topology templates. These constraints drive the routing of nets on the printed circuit board. You run preroute and postroute signal simulations to analyze the PCB for reflection, crosstalk, and other high-speed design factors.
Learning Objectives
After completing this course, you will be able to:
Create, extract and explore topologies
Run solution space analysis
Create an electrical constraint set
Apply constraints to drive placement and routing
Run postroute DRC check
Use template revision to update the ECSet applied to the nets
Analyze nets on the routed board design for signal integrity
Create estimated crosstalk constraints
Create a DesignLink between boards and use it to run multiboard simulation
Software Used in This Course Allegro Sigrity SI Base
Software Release(s) SPB17.2-2016QIR5
Modules in this Course
Introduction to Allegro Sigrity SI
Simulation Model Assignment
Topology Extraction
SigXplorer Basics
Sweep Simulations and Constraint Setting with SigXplorer
Constraint Floorplanning
DesignLink Creation
Postroute Analysis
Impedance and Coupling Checking
Estimated Crosstalk
Differential Pairs
The EMS2D Field Solver
Audience
Electrical Engineers
PCB Designers
Prerequisites
You must have
A familiarity with digital and analog circuit design methodology
A working knowledge of PCB signal analysis and transmission line theory
