DDR4 becomes pretty common high-speed source-synchronous interface. We are inviting you to attend half a day workshop that discuss and show DDR4 post-layout simulations with non-ideal power conditions. Synchronous design performance metrics including eye diagrams with detailed timing measurements and compliance kits vs JEDEC standard are available as outputs.
Audience
Electrical Engineers and Signal Integrity engineers who wish to learn how to analyze DDR4 interface using Sigrity SystemSI-Parallel Bus Analysis DDR4 Compliance Kit
