|
|
|
|
This hands-on workshop guides you through the Allegro/OrCAD ECAD-MCAD/3D Seamless solution.
It will present efficient and seamless ECAD-MCAD collaboration and PCB Editor Interactive 3D Canvas which reduces unnecessary ECAD-MCAD iterations and empower the PCB designer.
More Details
This hands-on workshop helps to understand the process of working with Constraint manager (CM) interface and defining constraints in OrCAD Capture CIS.
More Details
This half a day workshop will assist Electrical Engineers to communicate with Allegro/OrCAD PCB Layout designers. It covers basic knowledge on GUI and daily tasks like coloring, measurements, crossprobing between OrCAD Capture schematic drawing and Allegro/OrCAD PCB layout, creation of basic mechanical drawing, pre-placement of critical components.
More Details
This workshop will highlight the issues that have been traditionally found in the cycle between design and sign-off to manufacturing and will make the user aware of the time savings in catching these issues earlier in the cycle.
More Details
Doing impedance, return path and crosstalk analysis within PCB layout canvas for quick identification of impedance discontinuities and to identify if the impedance meets the defined constraints or not, ensure proper reference plane adherence, detection of signals crossing voids and stitching via constraint defines valid radius from center of signal via
More Details
Are you designing PCIe Gen4 and want to be sure that you channel passes JEDEC standard? Join the workshop that explores the use of Compliance Kit for PCIe 4. These kits come preloaded with various compliance test bench templates to help get started very quickly. Most of the major compliance checks are built in the compliance kit, eliminating all the work setting up the simulation test criteria.
More Details
DDR4 becomes pretty common high-speed source-synchronous interface. We are inviting you to attend half a day workshop that discuss and show DDR4 post-layout simulations with non-ideal power conditions. Synchronous design performance metrics including eye diagrams with detailed timing measurements and compliance kits vs JEDEC standard are available as outputs.
More Details
Traditionally, IPC provides a manual procedure to estimate peak board temperature. However, it is based on a simple model and is often too pessimistic, resulting in overdesign and unnecessary cost increase.
Integrated power/thermal co-simulation provides engineers with accurate design margins and lower manufacturing costs and can accurately assess the safety issue.
More Details
|
|
|
|
|
|
|
|
