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Package Design

Market demand for more functionality is driving the move to multi-layer flip-chip packaging to accommodate high-pin-count designs. To efficiently design these complex packages requires a sophisticated implementation tool that addresses both electrical and physical constraints. Cadence® IC package design technology is recognized worldwide for its efficient, flexible, and reliable implementation of dense, advanced package designs. Integrated signal and power integrity analysis ensures that electrical and physical challenges can be jointly addressed throughout the design cycle. Using Cadence IC package design technology, designers can meet compressed schedule demands with first-pass success.

Features

  • Supports a full front-to-back physical implementation flow for IC package design
  • Determines the best package and substrate options early in the IC design cycle
  • Provides comprehensive design rule and electrical constraint-driven layout
  • Incorporates design for manufacturing (DFM) methodologies
  • Improves design flow with intrinsic support for all industry standards
  • Models entire design in 3D with the optional Cadence 3D Design Viewer

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  • Address38 HaBarzel St. Tel Aviv 6971054 Israel
  • Tel(972) 3 6444416
  • Fax(972) 3 6444462
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