- Provides schematic and HDL/Verilog design input
- Assigns and manages high-speed design rules
- Supports net classes, buses, extended nets, and differential pairs
- Eliminates rework with powerful library creation and management
- Allows synchronization of logical and physical design
- Enables multi-user parallel development with systematic version control
- Integrates smoothly into pre-layout simulation and signal analysis
- Supports customizable user interface and enterprise deployment