OrCAD/Allegro FPGA System Planner

The FPGA Model Library included incorporates pin assignment and electrical rules specified by FPGA device vendors—ensuring vendor-defined electrical usage rules of FPGAs are strictly adhered to.

Generate and read supported FPGA vendors’ pin assignment constraint files, enabling the FPGA designer to evaluate pin assignments against the functional needs of the FPGA.

A built-in DRC engine incorporates the rules provided by FPGA vendors for pin assignment, reference voltages, and terminations—preventing PCB physical prototype iterations.

Shorten the time required to create pin assignments for a large number of FPGAs and quickly create DRC accurate FPGA pin assignments.

Specify connectivity between components within the FPGA sub-system at a higher level.