Support & Training
Allegro Sigrity System SI - Serial Links
Full-channel 3D Signal Integrity Analysis Including Non-ideal Power Effect of Multi-Gigabit Serial Link Interfaces (PCIe, Xaui, SATA, Infiniband, USB 2/3, HDMI, and more) with Allegro Sigrity SystemSI
This award-winning chip-to-chip analysis solution focuses on high-speed SerDes designs such as PCIe, HDMI, SFP+, Xaui, Infiniband, SAS, SATA, USB, and more. It makes early assessments using basic templates. Support for industry-standard IBIS AMI transmitter and receiver models enable simulations of channel behavior for serial links with chips from multiple suppliers. Chip model developers have access to techniques that assist them in model development. Models of multiple packages, connectors, and boards can be added to reflect the entire channel. Simulations identify crosstalk issues and show the effectiveness of chip-level clock and data recovery (CDR) techniques.
Full-channel frequency and time domain simulations including millions of bits of data confirm overall bit-error rate (BER) to determine if jitter and noise levels are within specified tolerances. This workshop will help you to manage your SerDes design complexities when you are force to deviate from the recommended vendor guidelines while maintaining your timing margin requirements, noise levels, and design tradeoffs. This is essential to emulate real hardware behavior to ensure first time success.
During this lab-intensive workshop, you’ll learn how to:

» Perform detailed SI analysis of high-speed serial links 
» Perform die-to-die analysis pre-layout, post-layout, or anywhere in-between
» Concurrently evaluate SI effects such losses, reflections, crosstalk, and SSO
» Observe the impact of non-ideal power delivery system effects on system behavior
» Develop, test and utilize IBIS AMI Tx and Rx models for serial link analysis
» Quantify the bit error rate (BER) and performance of complex SerDes channels
» Reduce costs and time by identifying potential problems early
» Verify interfaces to be compliant with JEDEC-based measurements performance standards kits
Related Info

Who should attend:

» Signal integrity specialists
» Design engineers
» Engineering managers
» Project managers





Sigrity SystemSI Single channel Analysis
Channel Templates, Components (Jitter, Noise, AMI FFE and DFE), Eye and Running

Sigrity SystemSI Cross Talk Channel Analysis

Channel Templates, Each Channel Components (Jitter, Noise, AMI FFE and DFE) and Running (AC Sweep, Statistical Xtalk)
Sigrity AMI Models Model Design, Model Configuration (Description, Parameters, Algorithms)
Sigrity SystemSI Advanced Capabilities Sweeping Manager, S-Parameters Extraction, Block Sensitivity (Normalized Jitter and Noise, 2D and 3D eyes and other curves)

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