Signal Integrity using Allegro PCB SI
During this lab-intensive workshop, you’ll learn how to:

» Basics of using SI analysis on Allegro PCB Environment 
» Creating basic pre-layout topology

»Stack-up Aware topology: Same stack-up data as board, loading and managing stackups, trace model selection based on stack-up

»Simulating DDR topology

»Sweeping Analysis
» Differential Pair topology and Eye Measurements
» Creating Electrical Constraints Sets  
» Constraints Driven Placement and Routing
» Post layout analysis: extract topology and simulation 

Related Info

Who should attend:

» Hardware Engineers and Managers who would like to learn the benefits of using SI Analysis
» PCB Designers who need to learn using SI on Allegro PCB Editor environment





Understanding Allegro PCB SI environment and IBIS models

Pre-Layout simulation and X-talk analysis

Creating basic topology, Stack-Up Aware SigXplorer and Estimated Cross Talk

Pre-Layout simulation

Simulating DDR topology and Sweeping Analysis

Pre-Layout simulation

Creating Differential Pair topology, Eye Measurements, Set Constraints and Constraints Driven Placement and Routing  

Post-Layout simulation

Topology Extraction, Running Simulation and exploration analysis, including Play&Fun: trying to improve the signal performance on your own.

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