EDAis Solutions
Timing Designer
The Timing’s Right
The timing`s right. That`s what designers expect and deserve. TimingDesigner® is the interactive timing analysis tool users trust to deliver fast and accurate results for timing critical designs. TimingDesigner is ideal for high-speed, multi-frequency designs where it is essential to accurately model and analyze signal relationships between devices on a board or between embedded functions on an ASIC or programmable IC. It can evaluate comprehensive sets of timing alternatives and provide direction to the most complex of timing challenges, enabling designers to manage and monitor timing margins through the design process.

Why TimingDesigner?

TimingDesigner excels in using an intuitive timing diagram approach for developing specifications to drive the design process, analyzing timing to answer critical design questions, and documenting results to clearly illustrate and communicate the design implementation.

Specify. Evaluating alternatives is key to developing specifications that can accurately convey design details and timing budgets. TimingDesigner supports the early investigation of timing options and provides a straightforward means to clearly specify the sequence of events and timing relationships required for modules or subsystems to communicate as expected.

Analyze. Interfaces between embedded processors, memory, and logic functions on a chip or between devices on a circuit board are often the source of difficult-to-locate timing violations, especially for high-speed designs. TimingDesigner`s robust timing engine uses a timing diagram specification to accurately analyze parameters and identify violations that may otherwise go undetected until late in the design process. The ability to quickly evaluate design alternatives and compute worst-case timing margins makes TimingDesigner an excellent choice to help develop solutions for specific problem areas.

Document. TimingDesigner delivers the ability to clearly and accurately communicate design details by exporting or linking timing diagram files generated during the design process through OLE support or in its native format. The standard, easy-to-interpret format of timing diagram specifications improves the communication of complex design information

Key Features:


Easy-to-use timing diagram editor enables rapid specification of design requirements including: timing constraints, cause-and-effect relationships, delays, and sequence protocols.


Dynamically linked timing spreadsheet with patented technology allows accurate modeling of complex delay and constraint effects.


Powerful timing analysis engine quickly identifies worst-case timing margins, allowing users to focus on trouble spots and make accurate design partitioning decisions.


Instant updates of intelligent timing diagrams support quick evaluation of design alternatives.


Robust project manager organizes component diagrams within a single project tree and eases the management and exchange of timing data among project team members.


Extensive import/export support eases exchange of waveform and timing data between tools used in the design flow.

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EDA Integrity Solutions Ltd. Address: 3 Hanechoshet St. Tel Aviv 6971068 Israel Tel: (972) 3 6444416 Fax: (972) 3 6444462
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