Allegro Package SI

Virtual interconnect exploration and simulation

Allegro Package SI offers powerful simulation for source synchronous and serial interfaces. The embedded 3D field solver resolves electrical issues early and performs extensive post-layout debugging.

Cadence® Allegro® Package SI performs direct read/write to the design database to achieve accurate prototyping without time-consuming setup, and directly incorporates the results. By providing key indicators early in the design process, it helps engineers make difficult tradeoff decisions. A graphical topology simulator/editor allows engineers to compare different electrical routing strategies, optimize design rules, and develop S-Parameter models. Adding a partner-supplied Apache Design Solutions 3D field solver provides accurate extraction. Allegro Package SI can also be used as a plug-in for chip/package IR drop analysis when used in conjunction with VoltageStorm® Power Verification.

  • Streamlines virtual prototyping, interconnect exploration, analysis, and modeling
  • Performs topology editing and solution space exploration with SigXplorer
  • Determines the best substrate options early in the design cycle
  • Includes SPICE-based simulation
  • Allows integration with the Apache-DA PakSI-E 3D field solver
  • Provides hierarchical constraint management
  • Enables virtual substrate editing and post-layout debugging
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