Allegro Sigrity System SI - Parallel Bus
Power-aware Signal Integrity Sign-off Implementation of Source-Synchronous Parallel Interfaces (DDRx-Memory) with Allegro Sigrity SystemSI
This end-to-end analysis solution targets source-synchronous parallel interfaces such as designs with DDRx memory. Pre-layout capabilities (including an optional via wizard) enable work to begin with models that are quickly generated and connected. As the design is refined, more detailed models are swapped in to reflect actual hardware behavior. Concurrent simulation accounts for the effects of dielectric and conductor losses, reflections, inter-symbol interference (ISI), crosstalk, and simultaneous switching noise. These simulations are able to fully account for impacts associated with non-ideal power delivery system characteristics. Graphical outputs and post-processing options give designers insight that enables rapid system improvements.
This workshop will help you to manage your DDRx routing complexities when you are force to deviate from the recommended vendor guidelines while maintaining your timing margin requirements, noise levels, and design tradeoffs. This is essential to emulate real hardware behavior to ensure first time success.
During this lab-intensive workshop, you’ll learn how to:

» Perform detailed SI analysis of high-speed parallel buses
» Perform die-to-die analysis pre-layout, post-layout, or anywhere in-between
» Accurate handling of non-ideal power delivery system influences on SI, which can be the dominant cause of reliability problems
» Concurrently evaluate SI effects such losses, reflections, crosstalk, and SSO
» Observe the impact of non-ideal power delivery system effects on system behavior
» Improve design quality by identifying potential SSO problems in parallel buses
» Reduce costs and time by identifying potential problems early
» Verify interfaces to be compliant with JEDEC-based measurements performance standards kits
Related Info

Who should attend:

» Signal integrity specialists
» Design engineers
» Engineering managers
» Project managers




Sigrity SystemSI Parallel Bus Analysis: Pre-layout feasibility, Topology exploration, Non-power‒aware PCB model exploration, Transmission line editor, Via modeler, Using simple IBIS models

Sigrity PowerSI Board Extraction: BRD to SPD database translation, Model setup, Decap modeling, Power-aware PCB model extraction, Input impedance and S-parameter study

Sigrity SystemSI Parallel Bus Analysis: Post-Layout Analysis, Building a power-aware topology, Using power-aware IBIS models, Using power-aware PCB models, Time domain SSN analyses

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