FPGA-PCB co-design with FSP
FPGA rules driven FPGA-PCB co-design with FPGA System Planner
Integrating today’s FPGAs with their many different types of assignment rules and user-configurable pins on PCBs is time consuming and extends design cycles. Often the pin assignment for these FPGAs is done manually at a pin-by-pin level in an environment that is unaware of the placement of critical PCB components that are connected to FPGAs and without understanding the impact to PCB routing. This workshop will highlight the benefits of using Cadence FPGA Systems Planner which replaces manual and error-prone processes with correct by construction I/O optimization enabling FPGA/PCB co-design process
During this lab-intensive workshop, you’ll learn how to:

» Enable an FPGA/PCB co-design process accelerating integration of FPGAs with Allegro PCB design
» Eliminates unnecessary, frustrating design iterations during the PCB layout process
» Eliminates unnecessary physical prototype iterations due to FPGA pin assignment errors
» Reduces PCB layer count through placement-aware pin assignment and optimization
» Enables interface-based connectivity definition for the FPGA system
» Enables placement-aware pin assignment synthesis that is FPGA-DRC accurate
» Automatic schematic creation using symbol generated for a specific FPGA design or from corporate library
» I/O optimization and pin swapping in the PCB design process including components orientations
Related Info

Who should attend:

» FPGA Designers
» Design engineers
» Project managers



Overview of FPGA System Planner

Creating an FSP Model

Placing Components and Establishing Connections

Protocols and Interfaces
I/O Synthes
Generating OrCAD Capture Schematics
Load FSP Project in Allegro PCB & Place FPGA Design
FPGA Pin Optimization
Verify & Synchronize PCB changes with the FSP Design

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