Support & Training
Allegro PCB SI Power Integrity

During this lab-intensive workshop, you`ll learn how to:

» Incorporate Power Integrity techniques in your Engineering design Environment

» Run Power Integrity Electrical Analysis on your PCB design.

» Explore Power Integrity effects of capacitors, placement and PCB stack-up strategies.

» Identify potential problems of high frequency noise in different areas of the PCB

» Free expensive PCB placement space by removing unnecessary Capacitors

» Identify the correct design solutions early in the design cycle.

Related Info

Who should attend:

» Hardware and Diagnostic Engineers designing and verifying PCB systems.
» Hardware Validation Engineers designing Evaluation and Reference PCB designs.
» Engineering and CAD managers who wish to implement new board design methodologies.
» PCB Layout Designers


Subject Details
Decoupling Theory Present decoupling theory, current decoupling design techniques and limitations
Allegro PI option (Power Integrity) Present the Cadence SPECCTRAQuest Power Integrity Product
Guided Hand-on tutorial Take a guided tour through a practical Power Integrity design flow
Hands on experience Verify Power Integrity design and experiment with different strategies of capacitors selections & placement, stack-up manipulations, and area shapes effects.
Closing session Summary

To Register click here.

 |  Home |  Cadence Solutions  |  EDAis Solutions  |  Partners  |  Services  |  Support & Training  |  News & Events  |  About Us  |  Stay In Touch  |  Favorite  | 
EDAis-Integrity Solutions Ltd.- © All Rights Reserved
EDA Integrity Solutions Ltd. Address: 3 Hanechoshet St. Tel Aviv 6971068 Israel Tel: (972) 3 6444416 Fax: (972) 3 6444462
  InterDeal Development