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Virtual interconnect exploration and simulation
Allegro Package SI offers powerful simulation for source synchronous and serial interfaces. The embedded 3D field solver resolves electrical issues early and performs extensive post-layout debugging.
 Cadence® Allegro® Package SI performs direct read/write to the design database to achieve accurate prototyping without time-consuming setup, and directly incorporates the results. By providing key indicators early in the design process, it helps engineers make difficult tradeoff decisions. A graphical topology simulator/editor allows engineers to compare different electrical routing strategies, optimize design rules, and develop S-Parameter models. Adding a partner-supplied Apache Design Solutions 3D field solver provides accurate extraction. Allegro Package SI can also be used as a plug-in for chip/package IR drop analysis when used in conjunction with VoltageStorm® Power Verification.
Features/Benefits
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Streamlines virtual prototyping, interconnect exploration, analysis, and modeling
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Performs topology editing and solution space exploration with SigXplorer
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Determines the best substrate options early in the design cycle
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Includes SPICE-based simulation
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Allows integration with the Apache-DA PakSI-E 3D field solver
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Provides hierarchical constraint management
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Enables virtual substrate editing and post-layout debugging
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Download Datasheet
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