Allegro Package Designer
Complete 3D co-design capabilities

Allegro Package Designer provides true integration with IC development in a physical co-design environment to help engineers make strategic tradeoffs earlier and with greater confidence.

Cadence® Allegro® Package Designer integrates with First Encounter® Silicon Virtual Prototyping to deliver chip-level I/O feasibility planning capabilities in an industry-proven co-design methodology. Data integration with First Encounter technology provides mask accuracy in the RDL routing and improves I/O padring optimization, substrate interconnect design, extraction, modeling, and signal integrity analysis. The final design output provides automatic system-level handoffs for PCB design.

  • Supports a full front-to-back IC/package physical co-design flow
  • Determines the best package and substrate options early in the IC design cycle
  • Provides comprehensive design rule- and electrical constraint–driven layout
  • Incorporates design for manufacturing (DFM) methodologies
  • Optimizes I/Os at the die bump level with a package-driven flow
  • Improves design flow with intrinsic support for all industry standards
  • Models entire design with Cadence 3D Design Viewer
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EDA Integrity Solutions Ltd. Address: 3 Hanechoshet St. Tel Aviv 6971068 Israel Tel: (972) 3 6444416 Fax: (972) 3 6444462
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